1. Field of the Invention
The invention relates to memory devices.
2. Description of the Related Art
When manufacturing SRAM cells in deep sub-micron technologies characteristics, errors like instability, write fail and read fail are expected due to large statistical deviations of the SRAM cells. Since a recovery of the manufacturing errors is costly, designing memory peripheries only addressing the bit cells is not efficient. The memory periphery has to take the statistical deviations into account.
For example, due to a high sensitivity of memory cells with respect to statistical fluctuations of parameters of elements forming the memory cells, e.g. transistors, the write operation of e.g. SRAM cells limits the possibility of employing a low voltage technology (using e.g. VDD=0.75 V) for memory cells.
In order to access a memory cell, usually an access transistor coupling a bitline to the memory element is activated for e.g. transferring a certain potential representing an information value (e.g. a “0”) to the memory cell. However, e.g. a positive voltage variation across the access transistor may superimpose the certain potential. If the resulting potential at the memory cell exceeds a certain threshold determined by the low voltage technology (e.g. 0.35 V), then a write error occurs. For example, if the threshold voltage of the access transistor is sufficiently high, this can lead to the impossibility of writing the “0” into the cell.